1. Field
Exemplary embodiments of the present invention relate to a semiconductor device, and more particularly, to a semiconductor device having a buried bit line and a fabricating method thereof.
2. Description of the Related Art
Most semiconductor devices include transistors. For example, in a memory device such as a DRAM, a memory cell includes a MOSFET. In general, in a MOSFET, source/drain regions are formed at the surface of a semiconductor substrate, and with such an arrangement, a planar channel is formed between the source region and the drain region. Such a general MOSFET is referred to as a planar channel transistor.
As advancements in integration and performance for a memory device are being made, MOSFET fabrication is reaching physical limits. For example, as the size of a memory cell shrinks, the size of a MOSFET such as the channel length thereof shrinks. If the channel length of a MOSFET is shortened, data maintaining properties are likely to deteriorate.
To address the above discussed features, a vertical channel transistor has been suggested in the art. In the vertical channel transistor (VCT), a source region and a drain region are formed on respective ends of a pillar. Any one of the source region and the drain region may be connected with a bit line. The bit line is formed by being buried in a trench defined between pillars, and accordingly, is referred to as a buried bit line (BBL).
Two memory cells each including a vertical channel transistor (VCT) and a buried bit line (BBL) are adjacent to one buried bit line (BBL). Therefore, the buried bit line (BBL) is formed in a space (trench) between cells, and an OSC (one-side-contact) process is performed to connect one cell with one buried bit line (BBL). The OSC process is a process for allowing each buried bit line (BBL) to be brought into contact with any one of two adjacent cells. Thus, the OSC process is also referred to as a single-side-contact (SSC) process. Generally, in a memory device such as a DRAM which adopts a planar channel transistor, in order to connect a planar channel transistor with a bit line, a contact plug process with a high aspect ratio is used. Conversely, in the case of adopting a vertical channel transistor and a buried bit line, since the vertical channel transistor and the buried bit line may be brought into direct contact with each other, a contact plug process is not necessary. Hence, because it is not necessary to connect a contact plug, the parasitic capacitance of the bit line may be reduced.
FIG. 1 is a cross-sectional view illustrating a buried bit line formed according to the conventional art.
Referring to FIG. 1, a plurality of bodies 14, which are separated by trenches 13, are formed on a semiconductor substrate 11. The bodies 14 are formed through etching using a hard mask layer 12. A protective layer 15 is formed on the sidewalls of the bodies 14 and on the surfaces of the trenches 13. Open parts 17 are defined in the protective layer 15 through an OSC process. Each open part 17 opens any one sidewall of each body 14. Buried bit lines 16 are formed to partially fill the trenches 13. The buried bit lines 16 are connected with the bodies 14 through the open parts 17. Each buried bit line 16 is connected with any one of two adjacent bodies 14. While not shown in the drawing, the upper portion of each body 14 includes a pillar in which source/drain regions and a channel of a vertical channel transistor are formed.
As can be seen from FIG. 1, in order to connect each buried bit line 16 to the sidewall of any one of the adjacent bodies 14, an OSC process is adopted. In order to realize the OSC process, various methods such as a liner layer and a tilt ion implantation process, an OSC mask process and the like have been proposed.
However, these methods fail to form a uniform and reproducible OSC structure due to difficulties in manufacturing processes. Also, as high integration of memory devices continue, the distance between adjacent buried bit lines 16 becomes narrow and parasitic capacitance CB between adjacent buried bit lines 16 increases. Since the buried bit lines 16 are brought into contact with the bodies 14, the parasitic capacitance CB between buried bit lines 16 is substantially capacitance between the body 14 and the buried bit line 16. Accordingly, because the distance between adjacent buried bit lines 16 becomes smaller, the parasitic capacitance CB increases significantly.
As the parasitic capacitance CB between buried bit lines increases, the normal operation of a device becomes difficult to obtain.